A liquid crystal display (“LCD”) device forms images by passing polarized light through small cells that vary their light-transmission characteristics according to electrical charges applied to the cells. Comparing with conventional cathode ray tube (“CRT”) display devices, LCDs provide superior display quality, require lower operation voltage, consume less power, and occupy less space. As a result, liquid crystal display has become one of the major display technologies today. In fact, liquid crystal displays have been employed in various types of systems, such as laptop and desktop computers, personal digital assistants (PDAs), car navigation systems, projectors, and cellular phones.
A liquid crystal display panel generally includes an array of active pixel elements, such as transistors. Color filters accompanying individual displaying pixels enable a color display. As an example, a display array may include scanning lines formed horizontally along rows of pixels, and signal or data lines formed FINNEGAN vertically along columns of pixels. Individual transistors, such as thin-film transistors (TFTs), are formed at or near the intersections of the scanning lines and data lines. The transistors operate according to video signals supplied through the scanning and data lines to control how images are displayed by pixels.
In general, the major components of a liquid crystal display include an interface integrated circuit (“IC”) for communicating with a source of video signals, a timing application-specific-integrated-circuit (“ASIC”) controller, data drivers, scan drivers, a display panel with passive devices thereon, and a backlight unit. The interface IC communicates with and receives data from a data source, such as a motherboard in a desktop or laptop computer. The timing ASIC controller receives data from the interface IC and sends display data to the scan and data drivers. The data drivers generate video signals and deliver the video signals to the pixels in the display panel to drive the pixels to display video images. In some designs, the timing ASIC controller also provides a scaling function to enable switching among two or more different resolutions.
FIG. 1 illustrates the operation of a single data driver 10. Data driver 10 has a clock input, load input, and RGB (red-green-blue) data input. Data driver 10 has two cascade terminals that can be coupled to other data drivers or devices. Data driver 10 samples RGB data according to the clock input and generates signals, such as analog video signals for controlling the pixels. Taking a liquid crystal display for a laptop computer as an example, the size of the liquid crystal display may vary from 12 to 15 inches; the resolution may vary from 640×480 to 1600×1200; and the pixel clock for scanning lines may vary from 50 to 100 MHz.
Generally, a driver drives a certain number of channels or pixels but does not handle all the pixels on one display line. The number of pixels each driver drives is usually far smaller than the number of pixels that a liquid crystal display has in a single display line or scan line. Therefore, most liquid crystal displays employ a design of pooling together multiple data drivers and jointly operate the multiple data drivers to receive and process data. Generally, the multiple data drivers drive all of the pixels in the liquid crystal display in a line-by-line manner.
In driving a line of pixels, drivers usually operate jointly in a cascaded configuration. FIG. 2 illustrates conventional cascaded data drivers. The structure consists of “n” data drivers that are cascaded through their cascading terminals to drive all of the pixels of a liquid crystal display. Here, each data driver receives data to drive M channels or pixels, with each pixel acting as a complete RGB display unit. The total number of pixels in a display line is, therefore, the total number of pixels driven by all of the data drivers, namely n×M.
Under the cascaded configuration, driver #0 receives a first group of display data at the beginning of a display line. When driver #0 is full, it sends out a signal to the next driver, driver #1. Driver #1 then starts to receive the next set of display data. When driver #1 is full, it sends out a signal to a subsequent driver, driver #2. All the subsequent drivers, drivers #2 to #n−1, then conduct the same operation until the data for a full display line are received by the cascaded data drivers.
More specifically, driver 10 in FIG. 1 is triggered to operate by a clock signal through the clock-in terminal, by a triggering pulse through a cascade-in terminal, or by both. Based on this configuration, driver #0 in FIG. 2 latches a unit of display data, such as RGB image data, at each rising edge of the clock signal. After a number of clock cycles, the register array of driver #0 becomes full and driver #0 then sends a signal to the next driver, driver #1, through the cascade-out terminal of driver #0. Once driver #1 receives the signal through its cascade-in terminal, it starts to receive the next group of data until the register array of driver #1 becomes full.
Referring to FIG. 3, a conventional design of a liquid crystal display employs a single clock in a timing ASIC controller 12 to provide a clock signal to all of the data drivers, drivers #0 to #n−1. The conventional design requires a single clock to have the capability to drive several cascaded data drivers, such as eight, ten, twelve, or fourteen cascaded data drivers. The clock also has to deliver signals of sufficient level and strength to the clock input pin of each data driver. Due to the total amount of load imposed by the input load of all input pins, the clock source must have a high output load driving capability, a term known as “fan-out.”
A clock with a higher fan-out, however, generates significant electromagnetic radiation that causes electromagnetic interference (EMI) with other devices or circuits. An excessive level of electromagnetic radiation may significantly interfere with the operation of other electronic devices to result in deteriorated performance of electronic devices within the proximity of the LCD. In addition, high EMI may also prevent the liquid crystal display from meeting certain safety and operational standards, such as the EMI standards established by the U.S. Federal Communications Commission (FCC).
To solve these problems, a dual or multiple clock design is developed and implemented in some liquid crystal displays. FIG. 4 provides an example of a dual clock design for a liquid crystal display. Data drivers #0 to #2n−1, which are used to be driven by a single clock in the conventional single-clock design, are now divided into two groups of equal numbers. Each group has “n” data drivers and is driven by a different clock. The illustrated system provides two clocks of smaller fan-out, pixel clocks 1 and 2, in the timing ASIC controller 14. These two clocks replace the single clock of a high fan-out illustrated in FIG. 3. The two clocks may provide continuous and synchronous clock signals to each group of data drivers. In general, the two clocks may operate to deliver synchronous signals and have overlapping signals near the center of the active “high” region of a valid display, as shown in FIG. 4B. Consequently, the two groups of drivers may alternate smoothly at a transitional point of data with the overlapping and synchronized clock signals.
The dual clock liquid crystal display system, however, requires each group of data drivers to drive an equal number of pixels, with each driver group being driven by one clock. The traditional dual clock system provides little flexibility in the design of the liquid crystal display, especially in the driving circuits. Also, the requirement of the traditional system considerably limits the possible implementations of data driver arrangements and creates significant obstacles for developing future generations of LCD systems. For example, current LCD system provides 800×600 pixels under the VGA mode, 1024×768 pixels under the SVGA mode, and 1280×1024 pixels under the SXGA mode. And future generations of LCD would provide an even larger number of pixels. The increased pixel dimension would make the traditional system less feasible.